Memory having a plurality of resistive non-volatile memory cells
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United States of America Patent
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May 23, 2017
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Mar 28, 2016
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Mar 28, 2016
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Abstract
A resistive non-volatile memory (NVMN) cell has three select transistors connected together in series. A first resistive element has a first terminal connected between first and second select transistors and a second terminal. A second resistive element has a first terminal connected between second and third transistors. In a first embodiment, the second terminals of the first and second resistive elements are connected to bit lines. In a second embodiment, the second terminals of the first and second resistive elements are connected to source lines. In the first embodiment, when the center select transistor is conductive, the first and second resistive elements become a resistor-divider. Each of the first and second resistive elements include a magnetic tunnel junction (MTJ).
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