Clock recovery techniques
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 2, 2017
Issued Date -
N/A
app pub date -
Mar 12, 2015
filing date -
Jun 27, 2005
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Clock recovery techniques (CRT) useful in a wide variety of communication systems based on wireless, optical and wireline links, include: a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality, a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing clocks, waveforms or messages, receiver synchronization techniques (RST) contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully