Semiconductor device and method of forming a power MOSFET with interconnect structure to achieve lower RDSON
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United States of America Patent
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May 2, 2017
Grant Date -
May 30, 2013
app pub date -
Jan 22, 2013
filing date -
May 15, 2008
priority date (Note) -
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Abstract
A semiconductor device has a substrate and gate structure over the substrate. A source region is formed in the substrate adjacent to the gate structure. A drain region in the substrate adjacent to the gate structure opposite the source region. An interconnect structure is formed over the substrate by forming a conductive plane electrically connected to the source region, and forming a conductive layer within openings of the conductive plane and electrically connected to the drain region. The interconnect structure can be formed as stacked conductive layers laid out in alternating strips. The conductive plane extends under a gate terminal of the semiconductor device. An insulating layer is formed over the substrate and a field plate is formed in the insulating layer. The field plate is electrically connected the source terminal. A stress relief layer is formed over a surface of the substrate opposite the gate structure.
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