Method and circuit for programming non-volatile memory cells of a volatile/non-volatile memory array
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United States of America Patent
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May 2, 2017
Grant Date -
Nov 10, 2016
app pub date -
Jan 7, 2015
filing date -
Jan 10, 2014
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Abstract
A memory array including: a first volatile memory cell including first and second cross-coupled inverters between first and second storage nodes; a first non-volatile memory cell including at least one resistive element that can be programmed to take one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.
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