First-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and processing method thereof
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United States of America Patent
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Apr 25, 2017
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app pub date -
Jan 8, 2014
filing date -
Aug 6, 2013
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Abstract
A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same are provided. The structure includes: a die pad (1); a lead (2); a chip (4) provided on a top surface of the die pad (1) by a conductive or non-conductive adhesive material (3); a metal wire (5) via which a top surface of the chip (4) is connected to a top surface of the lead (2); a conductive pillar (6) provided on the surface of the lead (2); and a molding material (7).
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