Semiconductor packaging structure and method for forming the same
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United States of America Patent
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Apr 11, 2017
Grant Date -
May 8, 2014
app pub date -
Nov 7, 2013
filing date -
Nov 8, 2012
priority date (Note) -
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Abstract
Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode.
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