Three dimensional memory control circuitry
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United States of America Patent
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Apr 11, 2017
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app pub date -
Oct 29, 2015
filing date -
Mar 26, 2012
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Abstract
An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
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