Methods and devices for stressing an integrated circuit

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United States of America Patent

PATENT NO 9618567
SERIAL NO

13641984

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Abstract

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Disclosed is in particular a device (2) for stressing an integrated circuit (1) including an electronic chip (10) mounted in a housing (12), the device including a source (20) of thermal stress. The device (2) also includes a thermally conductive coupling member (22), designed to be thermally coupled to the source (20) of thermal stress during the stressing operation. The coupling member (22) includes an end (220) whose geometry is suitable for being introduced into an aperture with a predefined geometry, to be made in the housing (12) of the integrated circuit (1) so as to thermally couple a coupling face (222) of this end (220) with a face (102) of the electronic chip (10).

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Patent Owner(s)

Patent OwnerAddress
EUROPEAN AERONAUTIC DEFENCE AND SPACE COMPANY EADS FRANCE37 BOULEVARD DE MONTMORENCY PARIS 75016

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Binois, Christian Francourville, FR 1 0
Douin, Alexandre Nanterre, FR 1 0
Moliere, Florian Paris, FR 2 6
Morand, Sebastien Boulogne-Billancourt, FR 5 10
Peyre, Daniel St Remy les Chevreuse, FR 1 0
Salvaterra, Gerard Clamart, FR 1 0

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