Digital delay-locked loop and locking method thereof
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United States of America Patent
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Apr 4, 2017
Grant Date -
Mar 23, 2017
app pub date -
May 23, 2016
filing date -
Sep 22, 2015
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Abstract
The digital delay-locked loop includes: a frequency divider, used to perform frequency division processing on a first clock-signal according to frequency division information, and output a second clock-signal; a signal-selector, used to select the first or second clock-signal as a third clock-signal according to the selection signal output; a delay line, used to delay the third clock-signal according to the delay control signal, and output a fourth clock-signal; a phase detector, used to receive the third and fourth clock-signals, perform phase detection processing, and output a phase detection judgment signal; and a state machine connected with the frequency divider, signal-selector, delay line and phase detector, used to adjust and control the frequency division information, the selection signal and the delay control signal output according to the phase detection judgment signal and a set state logic, to achieve that delay time of the fourth clock-signal relative to the first clock-signal.
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