ADC background calibration with dual conversions
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United States of America Patent
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Mar 28, 2017
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N/A
app pub date -
Jun 1, 2016
filing date -
Feb 9, 2016
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Abstract
An analog-to-digital converter (ADC) system can sample an input voltage for at least a first conversion into a first N1-bit digital value and to use the same input voltage sample for at least a second conversion into a second N2-bit digital value. A difference between a result of the first conversion and a result of the second conversion can be driven toward zero to adjust weights of one or more of the bits to calibrated values for use in one or more subsequent analog-to-digital conversions of subsequent samples of the input voltage. Shuffling, dithering, or the like can help ensure that at least a portion of the decision paths used in the second conversion are different from the decision paths used in the first conversion. Calibration can be performed in the background while the the ADC is converting in a normal mode of operation.
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