All digital phase locked loop
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United States of America Patent
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Mar 28, 2017
Grant Date -
Jan 19, 2017
app pub date -
Jul 15, 2016
filing date -
Jul 17, 2015
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Abstract
An all-digital phase-locked loop (AD-PLL) and related methods and computer readable medium are provided. The AD-PLL comprises a reference phase generator for receiving a digital signal and splitting the digital signal into an integer part and a fractional part, an estimator block for estimating a control signal, and a digital-to-time converter for receiving the estimated control signal and a reference clock signal and for deriving a delayed reference clock signal. The AD-PLL also includes a time-to-digital converter for receiving the delayed reference clock signal and a desired clock signal phase, and for deriving a fractional phase error. The estimator block receives the fractional phase error and determines the estimated control signal by correlating the fractional phase error with the fractional part, yielding a correlated signal, multiplying the correlated signal with its absolute value, and integrating the outcome of the multiplying to obtain the estimated control signal.
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