Delay locked loop (DLL) locked to a programmable phase
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 21, 2017
Grant Date -
N/A
app pub date -
Aug 31, 2015
filing date -
Sep 24, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully