Repeater insertions providing reduced routing perturbation caused by flip-flop insertions
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United States of America Patent
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Mar 21, 2017
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app pub date -
Mar 20, 2015
filing date -
Mar 20, 2015
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Abstract
System and method of automatically performing repeater insertions in physical design of an integrated circuit. Repeaters are inserted in interconnects in a staggered fashion and spaced apart to accommodate potential flip-flop insertions. The sufficient spacing between the repeaters in combination with the staggered pattern ensures that flip-flop insertions can be performed at any of the repeater locations without space limitation. When rerouting is needed following a flip-flop insertion on an interconnect, automatic rerouting is performed but restricted to a short and specified region along the interconnect. Thereby, the resulted alteration from the current routing configuration is minimal and deterministic.
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