Method and structure of three dimensional CMOS transistors with hybrid crystal orientations
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United States of America Patent
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Mar 14, 2017
Grant Date -
Sep 24, 2015
app pub date -
Mar 18, 2014
filing date -
Jul 8, 2008
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Abstract
A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.
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International Classification(s)
- H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....
- G01L:MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL ....
- B81C:PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE M....
- A61B:DIAGNOSIS; SURGERY; IDENTIFICATION
- G01P:MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, D....
- H03H:IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONA....
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