FinFET structures having silicon germanium and silicon channels
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United States of America Patent
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Mar 7, 2017
Grant Date -
Jul 30, 2015
app pub date -
Apr 3, 2015
filing date -
Jul 24, 2013
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Abstract
Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.
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