Systems and methods for random number generation using a fractional rate clock
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United States of America Patent
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Mar 7, 2017
Grant Date -
Jul 2, 2015
app pub date -
Dec 19, 2014
filing date -
Dec 26, 2013
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Abstract
Systems and methods are provided for generating a pseudo-random bit sequence at an output frequency using a clock signal operating at a first frequency that is lower than the output frequency. A first bit sequence of a particular type is generated using a clock signal operating at a first frequency. A second bit sequence is generated using the clock signal operating at the first frequency, where the second bit sequence is a delayed version of the first bit sequence. A delayed version of the first bit sequence is generated using the second bit sequence and another bit sequence, wherein the delayed version is delayed based on the particular type and a difference between the output frequency and the first frequency. The first bit sequence and the delayed version are combined to generate a pseudo-random bit sequence at the output frequency.
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