Phase locked loop with accurate alignment among output clocks
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United States of America Patent
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Feb 28, 2017
Grant Date -
Oct 13, 2016
app pub date -
Apr 5, 2016
filing date -
Apr 9, 2015
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Abstract
A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.
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