Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (SONOS) transistor and a gate oxide in a metal oxide semiconductor (MOS)
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 28, 2017
Grant Date -
N/A
app pub date -
Jan 16, 2015
filing date -
Dec 22, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor chip includes a base of a memory transistor in a first region of a substrate, and a base of a metal oxide semiconductor (MOS) transistor in a second region of the substrate. The base of the memory transistor includes a channel in a surface of substrate, a tunnel layer over the channel, and a nitride layer over the tunnel layer. The base of the MOS transistor includes a channel in the surface of substrate. The MOS transistor is coupled to the memory transistor through a shared diffusion region formed in the surface of substrate between the channel of the MOS transistor and the channel of the memory transistor. A plasma oxide overlying the nitride layer and the surface of the substrate to form a top oxide layer over the nitride layer and a gate oxide layer over the surface of substrate in the second region.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully