Integrated circuit with matching threshold voltages and method for making same
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United States of America Patent
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Feb 28, 2017
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N/A
app pub date -
Dec 3, 2015
filing date -
Jul 30, 2013
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Abstract
An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
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