Chip embedded package method and structure
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United States of America Patent
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Feb 28, 2017
Grant Date -
Apr 2, 2015
app pub date -
Jun 23, 2014
filing date -
Sep 29, 2013
priority date (Note) -
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Abstract
A chip embedded package method is provided by an embodiment of the present invention. The method comprises: etching metallic sinks on the thicker metal layer of each organic substrate; part of metallic sinks is used for packaging at least one chip, and other metallic sinks are used for via-holes; mounting the at least one chip into a metallic sink of each organic substrate via adhesive; flipping one organic substrate on another to form a combination; drilling blind-holes on both sides of the combination of the two organic substrates to pass through the adhesive; drilling via-holes to get through the combination of the two organic substrates, wherein the via-holes locates beyond the metallic sinks with chips; filling the blind-holes and via-holes with conductive medium through an electroplating process.
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