Circuits and methods of TAF-DPS based chip level global clock signal distribution
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United States of America Patent
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Feb 28, 2017
Grant Date -
N/A
app pub date -
Mar 26, 2015
filing date -
Mar 26, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
Circuits for distributing a global clock signal to all clock sinks on a chip for synchronous operation comprises 1) a plurality of synchronous clock areas (SCA), each SCA having a Time-Average-Frequency Direct Period Synthesis (TAF-DPS) clock source for generating a function clock, said TAF-DPS clock source has frequency synthesis and phase adjustment capabilities on its output of function clock; 2) a network for distributing a low frequency global clock signal to said plurality of synchronous clock areas, said global clock signal is used as reference for said TAF-DPS clock sources in all SCAs; 3) a plurality of clock sinks in each SCA, said clock sinks are driven by said function clock generated from said TAF-DPS clock source. Methods of distributing a low frequency global clock signal to all clock sinks in a chip for synchronous operation are also disclosed.
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International Classification(s)
- 2015 Application Filing Year
- G06F Class
- 57200 Applications Filed
- 45873 Patents Issued To-Date
- 80.20 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 5 Citation Count
- G06F Class
- 14.60 % this patent is cited more than
- 8 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Aug 28, 2028 |