Dual mode clock using a common resonator and associated method of use
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United States of America Patent
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Feb 28, 2017
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N/A
app pub date -
Mar 29, 2016
filing date -
Mar 29, 2016
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Abstract
An integrated circuit comprising, a resonator, a first clock circuit for generating a first clock signal having a first frequency in response to the resonator, a second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit of the integrated circuit, using a shift register based state machine and utilizing the inertia of the resonator to smoothly transition between the two oscillators, to provide a dual mode clock output signal.
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