Successive approximation ADC and control method thereof
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United States of America Patent
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Feb 21, 2017
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N/A
app pub date -
Aug 18, 2016
filing date -
Nov 13, 2015
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Abstract
Successive approximation ADC includes a digital-to-analog converter, a comparator, a comparison unit, a timing unit and a control logic circuit. The digital-to-analog converter converts a digital signal to a reference analog signal. The comparator compares an analog input signal with a reference analog voltage and generates a comparing signal. The comparison unit generates a comparison result signal according to the comparing signal. The timing unit generates a clock signal, and sequentially enables N supplementary clock signals corresponding to N bits when the comparison result signal is enabled. The control logic circuit updates the digital signal according to the comparing signal, and generates N bits of digital value sequentially from the most significant bit to the least significant bit, and then determines whether the digital value is valid according to whether the Nth supplementary clock signal corresponding to the least significant bit is enabled.
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