Test system and device
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United States of America Patent
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Feb 21, 2017
Grant Date -
Jan 15, 2015
app pub date -
Jun 25, 2014
filing date -
Jul 10, 2013
priority date (Note) -
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Abstract
An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing.
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