Modified flying adder architecture
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United States of America Patent
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Feb 14, 2017
Grant Date -
Jan 28, 2016
app pub date -
Jul 24, 2015
filing date -
Jul 25, 2014
priority date (Note) -
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Abstract
According to an embodiment, an improved flying adder circuit, comprises a fine clock, a coarse pulse clock, a rising edge triggered output connected to both the fine clock and the coarse pulse clock, a pulse clock connected to the rising edge triggered output, an adder, a 12-bit register situated to receive a signal from the adder and the pulse clock, and a single bit register situated to receive a signal from the pulse clock.
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