Coherence de-coupling buffer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 31, 2017
Issued Date -
N/A
app pub date -
Jun 3, 2014
filing date -
Apr 9, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A coherence decoupling buffer. In accordance with a first embodiment, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully