Identifying inversion error in logic equivalence check
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United States of America Patent
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Jan 17, 2017
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app pub date -
Mar 31, 2015
filing date -
Mar 31, 2015
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Abstract
System and method of checking logic equivalence following flip-flop insertions to identify paths with inversion errors. All the flip-flops in a gate-level netlist and the corresponding RTL design are treated as buffers in a logic equivalence check (LEC) tool. A logic mismatch of a path between the RTL design and the netlist indicates an odd number of inverters have been inserted in the path during a flip-flop insertion process. Accordingly, the identified path is adjusted to ensure an even number of inverters.
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