Interposer with embedded clock network circuitry
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United States of America Patent
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Jan 10, 2017
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N/A
app pub date -
Oct 4, 2013
filing date -
Oct 4, 2013
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Abstract
An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network.
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