Combination of TSV and back side wiring in 3D integration
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 10, 2017
Grant Date -
Jul 2, 2015
app pub date -
Dec 27, 2013
filing date -
Dec 27, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully