Method and apparatus for fabricating wafer by calculating process correction parameters

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United States of America Patent

PATENT NO 9543223
APP PUB NO 20140212817A1
SERIAL NO

13749740

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Abstract

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A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

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Patent Owner(s)

Patent OwnerAddress
QONIAC GMBH01307 DRESDEN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Habets, Boris Dreseden, DE 13 92

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