Memory device and signal processing circuit
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United States of America Patent
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Jan 3, 2017
Grant Date -
Jun 11, 2015
app pub date -
Feb 13, 2015
filing date -
May 20, 2011
priority date (Note) -
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Abstract
A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. The memory device includes a logic circuit including a first node, a second node, a third node, and a fourth node; a first control circuit connected to the first node, the second node, and the third node; a second control circuit connected to the first node, the second node, and the fourth node; a first memory circuit connected to the first node, the first control circuit, and the second control circuit; and a second memory circuit connected to the second node, the first control circuit, and the second control circuit.
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