Frequency multiplier based on a low dimensional semiconductor structure
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United States of America Patent
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Dec 27, 2016
Grant Date -
Feb 4, 2016
app pub date -
Mar 25, 2014
filing date -
Apr 23, 2013
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Abstract
A frequency multiplier based on a low dimensional semiconductor structure, including an insulating substrate layer, a semiconductor conducting layer arranged on the surface of the insulating substrate layer, an insulating protective layer arranged on the surface of the semiconductor conducting layer, an insulating carving groove penetrating the semiconductor conducting layer, an inlet electrode arranged on the side surface of the semiconductor conducting layer, and an outlet electrode arranged on the side surface corresponding to the access electrode is provided. The semiconductor conducting layer comprises two two-dimensional, quasi-one-dimensional, or one-dimensional current carrying channels near to and parallel to each other. The frequency multiplier has advantages that the structure is simple, the process is easy to implement, no extra filter circuit needs to be added, dependence on material characteristics is little, and the selection range of materials is wide.
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