DRAM error correction event notification
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 27, 2016
Grant Date -
Nov 19, 2015
app pub date -
May 15, 2014
filing date -
May 15, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully