High speed low voltage hybrid output driver for FPGA I/O circuits
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United States of America Patent
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Dec 20, 2016
Grant Date -
Aug 18, 2016
app pub date -
Feb 15, 2016
filing date -
Feb 18, 2015
priority date (Note) -
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Abstract
A hybrid input/output pad driver includes an input node in a first voltage supply domain coupled to a p-device driver in the second voltage supply domain and an n-device driver in the second voltage domain. A p-channel pullup transistor is coupled between a voltage potential in a third voltage domain and an input/output pad. Its gate is coupled to the output of the p-device driver. An n-channel pulldown transistor is coupled between ground and the input/output pad. Its gate is coupled to the output of the n-device driver. An n-channel pullup transistor has a source coupled to the input/output pad, a drain coupled to the voltage potential in the third voltage supply domain. An inverter in the second voltage supply domain is programmably connectable between the output of the p-driver circuit and the gate of the n-channel pullup transistor.
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