Contact structure and extension formation for III-V nFET
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 13, 2016
Issued Date -
N/A
app pub date -
May 21, 2015
filing date -
May 21, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully