Data transfer between clock domains
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United States of America Patent
Stats
-
Dec 6, 2016
Grant Date -
May 21, 2015
app pub date -
Jun 20, 2013
filing date -
Jun 27, 2012
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means (2) clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means (2) detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.
First Claim
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Family
International Classification(s)
- 2013 Application Filing Year
- H04L Class
- 23397 Applications Filed
- 19833 Patents Issued To-Date
- 84.77 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- H04L Class
- 8.87 % this patent is cited more than
- 9 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jun 6, 2028 |
