Semiconductor packaging structure and forming method therefor
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United States of America Patent
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Dec 6, 2016
Grant Date -
Feb 11, 2016
app pub date -
Jun 26, 2014
filing date -
Feb 24, 2014
priority date (Note) -
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Abstract
The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged on the bonding pads; lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins; the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins; a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames and exposing the external pins. By adopting the present invention, a transverse area occupied by the package structure is decreased, the volume of the entire package structure is correspondingly decreased, and the integration level of the package structure is improved. The present invention further provides a forming method of the semiconductor package structure.
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