Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment
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United States of America Patent
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-
Dec 6, 2016
Grant Date -
May 29, 2014
app pub date -
Apr 26, 2013
filing date -
Apr 26, 2012
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.
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|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jun 6, 2028 |
