Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture
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United States of America Patent
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Nov 29, 2016
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N/A
app pub date -
Aug 24, 2016
filing date -
Jun 14, 2015
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Abstract
A package can include a first, second and third semiconductor devices stacked in a first direction. A first semiconductor device can include a first through via between a first side and a second side opposite the first side of the first semiconductor device and a first circuit that provides a first reference potential at a first circuit output, electrically connected to the first through via in a normal mode of operation. A second semiconductor device can include a second through via, a second circuit, and a third circuit. A second circuit can be electrically connected to the first through via at the second side. A third circuit can provide a second reference potential and can be electrically connected to the second through via at the first side. The third circuit and the third semiconductor device can receive the second reference potential exclusive of the first semiconductor device.
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