Memory system controller including a multi-resolution internal cache
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United States of America Patent
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Nov 29, 2016
Grant Date -
Jun 4, 2015
app pub date -
Dec 3, 2013
filing date -
Dec 3, 2013
priority date (Note) -
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Abstract
A memory system comprising a non-volatile memory and a controller in communication with the non-volatile memory is disclosed. The controller may include a central processing unit (“CPU”) and an internal cache in communication with the CPU via a plurality of cache lines. The CPU is configured to utilize a first subset of the plurality of cache lines when accessing data stored in the internal cache at a first resolution. Additionally, the CPU is configured to utilize a second subset of the plurality of cache lines when accessing data stored in the internal case at a second resolution, where the first and second resolutions are different resolutions.
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