Semiconductor package, fabrication method therefor, and package-on package
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United States of America Patent
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Nov 22, 2016
Grant Date -
Jul 2, 2015
app pub date -
May 9, 2013
filing date -
May 25, 2012
priority date (Note) -
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Abstract
Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package includes an insulating substrate including a first through portion and a second through portion; a through wiring which fills the first through portion, and is located to penetrate the insulating substrate; a semiconductor chip which is located in the second through portion, and is electrically connected to the through wiring; a molding member molding the semiconductor chip and the insulating substrate; and a re-wiring pattern layer which is located at a lower side of the insulating substrate, and electrically connects the through wiring and the semiconductor chip.
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