External memory tagging and stack ordering of memory tags
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United States of America Patent
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Nov 22, 2016
Grant Date -
Aug 18, 2016
app pub date -
Feb 17, 2015
filing date -
Feb 17, 2015
priority date (Note) -
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Abstract
A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.
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