Method for forming interconnection structures
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United States of America Patent
Stats
-
Nov 15, 2016
Issued Date -
N/A
app pub date -
Nov 27, 2012
filing date -
Nov 27, 2012
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention provides a method for forming interconnection structures, including the following steps: providing a semiconductor wafer with a dielectric layer; forming a first recessed area for forming the interconnection structures and a non-recessed area on the dielectric layer; forming a second recessed area for forming dummy structures on the dielectric layer; depositing a barrier layer to cover the first and second recessed areas and the non-recessed area; depositing a metal layer to fill the first and second recessed areas and cover the non-recessed area; removing the metal layer on the non-recessed area to expose the barrier layer; and removing the barrier layer on the non-recessed area to expose the dielectric layer.
First Claim
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International Classification(s)
Cited Art Landscape
Patent Citation Ranking
- 2 Citation Count
- H01L Class
- 13.47 % this patent is cited more than
- 9 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | May 15, 2028 |
