Memory with bank-conflict-resolution (BCR) module including cache
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United States of America Patent
Stats
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Nov 15, 2016
Grant Date -
Dec 12, 2013
app pub date -
Mar 15, 2013
filing date -
Jun 6, 2012
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A memory device includes a block of memory cells and a cache. The block of memory cells is a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
MOSYS INC | 3301 OLCOTT ST SANTA CLARA CA 95054 |
International Classification(s)

- 2013 Application Filing Year
- G06F Class
- 48303 Applications Filed
- 43929 Patents Issued To-Date
- 90.95 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Miller, Michael J | Saratoga, US | 190 | 8256 |
# of filed Patents : 190 Total Citations : 8256 | |||
Patel, Jay | Los Gatos, US | 45 | 451 |
# of filed Patents : 45 Total Citations : 451 | |||
Sikdar, Dipak | Santa Clara, US | 3 | 26 |
# of filed Patents : 3 Total Citations : 26 |
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- 0 Citation Count
- G06F Class
- 0 % this patent is cited more than
- 9 Age
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