Memory with bank-conflict-resolution (BCR) module including cache

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United States of America Patent

PATENT NO 9496009
APP PUB NO 20130332665A1
SERIAL NO

13841025

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Abstract

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A memory device includes a block of memory cells and a cache. The block of memory cells is a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.

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Patent Owner(s)

Patent OwnerAddress
MOSYS INC3301 OLCOTT ST SANTA CLARA CA 95054

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  • 2013 Application Filing Year
  • G06F Class
  • 48303 Applications Filed
  • 43929 Patents Issued To-Date
  • 90.95 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances20132014201520162017201820192020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Miller, Michael J Saratoga, US 190 8256
Patel, Jay Los Gatos, US 45 451
Sikdar, Dipak Santa Clara, US 3 26

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3122144564193188710466053822701961379632401 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +010002000300040005000600070008000900010000110001200013000140001500016000

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