Memory with bank-conflict-resolution (BCR) module including cache
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United States of America Patent
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Nov 15, 2016
Grant Date -
Dec 12, 2013
app pub date -
Mar 15, 2013
filing date -
Jun 6, 2012
priority date (Note) -
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Abstract
A memory device includes a block of memory cells and a cache. The block of memory cells is a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.
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