Memory device
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United States of America Patent
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Nov 8, 2016
Grant Date -
Aug 25, 2016
app pub date -
Feb 11, 2016
filing date -
Feb 20, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
To provide a memory device where multiple pieces of multilevel data can be written and read. The memory device includes first to fifth transistors, first to fourth capacitors, first to fourth nodes, and first and second wirings. The first node is connected to the first capacitor and a gate of the first transistor, the second node is connected to the second capacitor and a gate of the second transistor, the third node is connected to the third capacitor and a gate of the third transistor, and the fourth node is connected to the fourth capacitor and a gate of the fourth transistor. Multiple pieces of multilevel data is written to the first to fourth nodes through the second to fifth transistors. The second to fifth transistors each preferably include an oxide semiconductor in a channel formation region.
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