Circuit arrangement and method for calibrating activation signals for voltage-controlled oscillators
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United States of America Patent
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Nov 1, 2016
Grant Date -
Dec 31, 2015
app pub date -
Nov 24, 2014
filing date -
May 23, 2012
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Abstract
In order to develop a circuit arrangement and also a method for calibrating at least one activation signal provided for a voltage-controlled oscillator such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed—that the respective number of clock cycles for at least one calibration oscillator and at least one reference oscillator associated with the calibration oscillator is counted by means of at least one clock cycle counter connected downstream of the calibration oscillator and the reference oscillator and a clock error resulting from the difference between these two numbers of clock cycles is integrated and—that the clock error is converted by means of at least one digital-to-analog converter connected downstream of the clock counter into analog tuning signals from which the calibrated activation signal is derived.
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