Method for fabricating FinFET with separated double gates on bulk silicon
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United States of America Patent
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Oct 25, 2016
Grant Date -
Aug 20, 2015
app pub date -
Oct 11, 2012
filing date -
Aug 29, 2012
priority date (Note) -
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Abstract
Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed. Further, the power consumption of the device can be further reduced through the special multi-threshold characteristic of the device with separated double gates.
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