Methods, systems, and computer readable media for address and data integrity checking in flash memory operations
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 25, 2016
Grant Date -
Mar 17, 2016
app pub date -
Sep 15, 2014
filing date -
Sep 15, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Methods, systems, and computer readable media for address and data integrity checking in flash memory operations are disclosed. One method includes, at a storage controller, generating, for an address unit, an address parity unit. The method further includes generating a command sequence including the address unit, the address parity unit, and an operation command specifying an operation to be performed on a flash memory array. The method further includes providing the command sequence to a flash memory device that includes the non-volatile memory array. The method further includes performing, by the flash memory device, an address integrity check on the address unit using the address parity unit. The method further includes determining whether or not to perform an operation specified by the command sequence based at least in part on a result of the address integrity check.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully