Power management with flip-flops
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United States of America Patent
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Oct 18, 2016
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N/A
app pub date -
Sep 24, 2015
filing date -
Sep 24, 2015
priority date (Note) -
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Abstract
An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.
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