Dynamic clock rate control for power reduction
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 11, 2016
Grant Date -
Sep 8, 2016
app pub date -
Mar 2, 2015
filing date -
Mar 2, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective, individual input and output buffer fill levels and processor busy statuses. Variable-rate clock generation circuitry may generate the variable-rate clock signals based on a common clock signal. Additionally, the variable-rate clock generation circuity may set or adjust the rates of variable-rate clock signals linearly in evenly-spaced increments and decrements.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully